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CYRF7936
2.4 GHz CyFiTM Transceiver
Features

Battery Voltage Monitoring Circuitry Supports coin-cell operated applications Operating voltage from 1.8V to 3.6V Operating temperature from 0 to 70C Space saving 40-pin QFN 6x6 mm package
2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio transceiver Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz - 2.483 GHz) 21 mA operating current (Transmit at -5 dBm) Transmit power up to +4 dBm Receive sensitivity up to -97 dBm Sleep Current <1 A DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps Low external component count Auto Transaction Sequencer (ATS) - no MCU intervention Framing, Length, CRC16, and Auto ACK Power Management Unit (PMU) for MCU Fast Startup and Fast Channel Changes Separate 16-byte Transmit and Receive FIFOs Dynamic data rate reception Receive Signal Strength Indication (RSSI) Serial Peripheral Interface (SPI) control while in sleep mode 4 MHz SPI microcontroller interface
Applications

Wireless Sensor Networks Wireless Actuator Control Home Automation White Goods Commercial Building Automation Automatic Meter Readers Precision Agriculture Remote Controls Consumer Electronics Personal Health and Fitness Toys
Applications Support
See www.cypress.com for development tools, reference designs, and application notes.
Logic Block Diagram
VREG L/D VBAT VIO IRQ SS SCK MISO MOSI VDD VCC PACTL
PMU
CyFi Radio Modem Data Interface and Sequencer
GFSK Modulator
RFP RFN RFBIAS
DSSS Baseband & Framer
SPI
RSSI Xtal Osc Synthesizer
GFSK Demodulator
RST XTAL XOUT GND
Cypress Semiconductor Corporation Document #: 001-48013 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 10, 2008
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CYRF7936
Functional Description
The CYRF7936 CyFiTM Transceiver is a Radio IC designed for low-power embedded wireless applications. Combined with Cypress's PSoC programmable system-on-chip and a CyFi network protocol stack, CYRF7936 can be used to implement a complete CyFi wireless system. Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
VBAT0 38 VREG 40 RST 34
Corner tabs
VDD 35
L/D 37
NC 36
NC 31
NC 39
NC 32
VIO 33
XTAL 1 NC VCC NC NC VBAT1 VCC VBAT2 NC 2 3 4 5 6 7 8 9
* E- PAD Bottom Side
30 29 28
PACTL / GPIO XOUT / GPIO MISO / GPIO MOSI / SDAT IRQ / GPIO
CYRF7936 CyFi Transciever 40 lead QFN
27 26
25 SCK 24 SS 23 NC 22 NC 21 NC
RFBIAS 10 11 RFP 12 GND 13 RFN 14 NC 15 NC 16 VCC 17 NC 18 NC 19 RESV 20 NC
Table 1. Pin Description - CYRF7936 40-Pin QFN Pin Number 13 11 10 30 1 29 25 28 27 24 26 34 Name RFN RFP RFBIAS PACTL XTAL XOUT SCK MISO MOSI SS# IRQ RST Type IO IO O IO I IO I IO IO I IO I Default I I O O I O I Z I I O I Description Differential RF signal to and from antenna. Differential RF signal to and from antenna. RF IO 1.8V reference voltage. Control signal for external PA, T/R switch, or GPIO. 12 MHz crystal. Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO. Tri-states in sleep mode (configure as GPIO drive LOW). SPI clock. SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode). Tri-states when SPI 3PIN = 0 and SS# is deasserted. SPI data input pin (Master Out Slave In), or SDAT. SPI enable, active LOW assertion. Enables and frames transfers. Interrupt output (configurable active HIGH or LOW), or GPIO. Device reset. Internal 10 kohm pull down resistor. Active HIGH, typically connect through a 0.47 F capacitor to VBAT. Must have RST = 1 event the first time power is applied to the radio. Otherwise the state of the radio control registers is unknown. PMU inductor/diode connection, when used. If not used, connect to GND. PMU boosted output voltage feedback. Decoupling pin for 1.8V logic regulator, connect through a 0.47 F capacitor to GND. VBAT = 1.8V to 3.6V. Main supply. VCC = 2.4V to 3.6V. Typically connected to VREG. Page 2 of 21
37 40 35 6, 8, 38 3, 7, 16
LVD VREG VDD VBAT(0-2) VCC
O Pwr Pwr Pwr Pwr
Document #: 001-48013 Rev. **
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CYRF7936
Table 1. Pin Description - CYRF7936 40-Pin QFN (continued) Pin Number 33 19 Name VIO RESV Type Pwr I NC Default IO interface voltage, 1.8-3.6V. Must be connected to GND. Connect to GND. Description
2, 4, 5, 9, 14, 15, NC 18, 17, 20, 21, 22, 23, 32, 36, 39, 31 12 E-PAD Corner Tabs GND GND NC
GND GND NC
Ground. Must be soldered to Ground. Do Not solder the tabs and keep other signal traces clear. All tabs are common to the lead frame or paddle which is grounded after the pad is grounded. While they are visible to the user, they do not extend to the bottom.
Functional Overview
The CYRF7936 IC is designed to implement wireless device links operating in the worldwide 2.4 GHz ISM frequency band. It is intended for systems compliant with worldwide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada), and TELEC ARIB_T66_March, 2003 (Japan). The CYRF7936 contains a 2.4 GHz CyFi radio modem which features a 1 Mbps GFSK radio front-end, packet data buffering, packet framer, DSSS baseband controller, and Received Signal Strength Indication (RSSI). CYRF7936 features a SPI interface for data transfer and device configuration. The CyFi radio modem supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). The baseband performs DSSS spreading/despreading, Start of Packet (SOP), End of Packet (EOP) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates. This enables the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both. It changes to lower data rates at longer distances or in high interference environments or both. In addition, the CYRF7936 IC has a Power Management Unit (PMU), which allows direct connection of the device to any battery voltage in the range 1.8V to 3.6V. The PMU conditions the battery voltage to provide the supply voltages required by the device, and may supply external devices.
Data Transmission Modes
The CyFi radio transceiver supports two different data transmission modes:

In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. In 8DR mode, DSSS is enabled and eight bits are encoded in each derived code symbol transmitted.
Both 64 chip and 32 chip Pseudo Noise (PN) codes are supported in 8DR mode. In general, lower data rates reduce packet error rate in any given environment.
Packet Framing
The CYRF7936 IC device supports the following data packet framing features: SOP Packets begin with a two-symbol Start-of-Packet (SoP) marker. The SOP_CODE_ADR PN code used for the SOP is different from that used for the "body" of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. Length This is the first eight bits after the SOP symbol, and is transmitted at the payload data rate. An EoP condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16. CRC16 The device may be configured to append a 16 bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver verifies the calculated CRC16 for the payload data against the received value in the CRC16 field. The seed value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 is checked against both the configured and zero CRC16 seeds.
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CYRF7936
CRC16 detects the following errors:

Any odd number of bits in error (irrespective of the location). An error burst as wide as the checksum itself.
Any one bit in error. Any two bits in error (irrespective of how far apart, which column, and so on).
Figure 2 shows an example packet with SOP, CRC16, and lengths fields enabled, and Figure 3 shows a standard ACK packet.
Figure 2. Example Packet Format
P re a m b le n x 16us 2 n d F ra m in g S y m b o l*
P
SOP 1
1 s t F ra m in g S y m b o l*
SOP 2
L e n g th
Packet le n g th 1 B y te P e rio d
P a y lo a d D a ta
C R C 16
*N o te :3 2 o r 6 4 u s
Figure 3. Example ACK Packet Format
P r e a m b le n x 16us 2 n d F r a m in g S y m b o l*
P
SOP 1
1 s t F r a m in g S y m b o l*
SOP 2
C RC 16
C R C fie ld fr o m r e c e iv e d p a c k e t. 2 B y te p e r io d s
*N o te :3 2 o r 6 4 u s
Packet Buffers
All data transmission and reception use the 16 byte packet buffers - one for transmission and one for reception. The transmit buffer allows loading a complete packet of up to 16 bytes of payload data in one burst SPI transaction. This is then transmitted with no further MCU intervention. Similarly, the receive buffer allows receiving an entire packet of payload data up to 16 bytes with no firmware intervention required until the packet reception is complete. The CYRF7936 IC supports packets up to 255 bytes. However, the actual maximum packet length depends on the accuracy of the clock on each end of the link and the data mode. Interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing.
Similarly, when receiving in transaction mode, the device automatically:

waits in receive mode for a valid packet to be received transitions to transmit mode, transmits an ACK packet transitions to the transaction end state (receive mode to await the next packet, and so on.)
The contents of the packet buffers are not affected by the transmission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action (as long as packets of 16 bytes or less are used). To transmit data, the MCU must load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware must retrieve the fully received packet in response to an interrupt request indicating reception of a packet.
Data Rates
The CYRF7936 IC supports the following data rates by combining the PN code lengths and data transmission modes described in the previous sections:

Auto Transaction Sequencer (ATS)
The CYRF7936 IC provides automated support for transmission and reception of acknowledged data packets. When transmitting in transaction mode, the device automatically:

1000 kbps (GFSK) 250 kbps (32 chip 8DR) 125 kbps (64 chip 8DR)
starts the crystal and synthesizer enters transmit mode transmits the packet in the transmit buffer transitions to receive mode and waits for an ACK packet transitions to the transaction end state when an ACK packet is received or a timeout period expires
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CYRF7936
Functional Block Overview
2.4 GHz CyFi Radio Modem
The CyFi radio Modem is a dual conversion low IF architecture optimized for power, range, and robustness. The CyFi radio modem employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in seven steps. The supply current of the device is reduced as the RF output power is reduced. Table 2. Internal PA Output Power Step Table PA Setting 7 6 5 4 3 2 1 0 Typical Output Power (dBm) +4 0 -5 -13 -18 -24 -30 -35
SPI communication may be described as the following:

Command Direction (bit 7) = `1' enables SPI write transaction. When it equals a `0', it enables SPI read transactions. Command Increment (bit 6) = `1' enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access. Otherwise the same address is accessed. Six bits of address Eight bits of data

The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active LOW Slave Select (SS#) pin must be asserted to initiate an SPI transfer. The application MCU can initiate SPI data transfers using a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes shown in Figure 4 through Figure 7 on page 6. The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as required. A burst transaction is terminated by deasserting the slave select (SS# = 1). The SPI communications interface single read and burst read sequences are shown in Figure 5 and Figure 6 on page 6, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 7 and Figure 8 on page 6, respectively. This interface may be optionally operated in a 3-pin mode with the MISO and MOSI functions combined in a single bidirectional data pin (SDAT). When using 3-pin mode, user firmware must ensure that the MOSI pin on the MCU is in a high impedance state except when MOSI is actively transmitting data. The device registers may be written to or read from one byte at a time, or several sequential register locations may be written or read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the device includes register files. Register files are FIFOs written to and read from using nonincrementing burst SPI transactions. The IRQ pin function may be optionally multiplexed onto the MOSI pin. When this option is enabled, the IRQ function is not available while the SS# pin is LOW. When using this configuration, user firmware must ensure that the MOSI pin on the MCU is in a high impedance state whenever the SS# pin is HIGH. The SPI interface is not dependent on the internal 12 MHz clock. Registers may therefore be read from or written to when the device is in sleep mode, and the 12 MHz oscillator disabled. The SPI interface and the IRQ and RST pins have a separate voltage reference pin (VIO). This enables the device to interface directly to MCUs operating at voltages below the CYRF7936 IC supply voltage.
Frequency Synthesizer
Before transmission or reception may begin, the frequency synthesizer must settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. The `fast channels' (less than 100 s settling time) are every third channel, starting at 0 up to and including 72 (for example, 0, 3, 6, 9 .... 69, 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception, CRC16 generation and checking, and EOP detection and length field.
Packet Buffers and Radio Configuration Registers
Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet. Configuration registers allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and so on.
SPI Interface
The CYRF7936 IC has an SPI interface supporting communication between an application MCU and one or more slave devices (including the CYRF7936). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. The SPI communications interface consists of Slave Select (SS#), Serial Clock (SCK), Master Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data (SDAT).
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CYRF7936
Figure 4. SPI Transaction Format
Byte 1 Bit # Bit Name 7 DIR 6 INC [5:0] Address Byte 1+N [7:0] Data
Figure 5. SPI Single Read Sequence
SCK SS
cmd addr
A5 A4 A3 A2 A1 A0
MOSI MISO
DIR 0
INC
data to mcu
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. SPI Incrementing Burst Read Sequence
SCK SS MOSI MISO
cmd
DIR 0 INC A5 A4
addr
A3 A2 A1 A0
data to mcu1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
data to mcu1+N
D5 D4 D3 D2 D1 D0
Figure 7. SPI Single Write Sequence
SCK SS
cmd addr
A5 A4 A3 A2 A1 A0 D7 D6
data from mcu
D5 D4 D3 D2 D1 D0
MOSI MISO
DIR 1
INC
Figure 8. SPI Incrementing Burst Write Sequence
SCK SS
cmd addr
A5 A4 A3 A2 A1 A0 D7 D6
data from mcu1
D5 D4 D3 D2 D1 D0 D7 D6
data from mcu1+N
D5 D4 D3 D2 D1 D0
MOSI MISO
DIR 1
INC
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CYRF7936
Interrupts
The device provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active HIGH or active LOW, and be either a CMOS or open drain output. The available interrupts are described in the section Register Descriptions on page 12. The CYRF7936 IC features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled or disabled. The contents of the enable registers are preserved when switching between transmit and receive modes. If more than one interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without the IRQ pin, by polling the status registers to wait for an event, rather than using the IRQ pin.
The output voltage (VREG) of the Power Management Unit (PMU) is configurable to several minimum values between 2.4V and 2.7V. VREG may be used to provide up to 15 mA (average load) to external devices. It is possible to disable the PMU and provide an externally regulated DC supply voltage to the device's main supply in the range 2.4V to 3.6V. The PMU also provides a regulated 1.8V supply to the logic. The PMU is designed to provide high boost efficiency (74-85% depending on input voltage, output voltage, and load) when using a Schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. However, reasonable efficiencies (69-82% depending on input voltage, output voltage, and load) may be achieved when using low cost components such as SOT23 diodes and 0805 inductors. The PMU also provides a configurable low battery detection function, which may be read over the SPI interface. One of seven thresholds between 1.8V and 2.7V may be selected. The interrupt pin may be configured to assert when the voltage on the VBAT pin falls below the configured threshold. LV IRQ is not a latched event. Battery monitoring is disabled when the device is in sleep mode.
Clocks
A 12 MHz crystal (30 ppm or better) is directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. The requirements to directly connect the crystal to the XTAL pin and GND are:

Low Noise Amplifier and Received Signal Strength Indication
The gain of the receiver can be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of the RX_CFG_ADR register. Clearing the LNA bit reduces the receiver gain approximately 20 dB, allowing accurate reception of very strong received signals (for example, when operating a receiver very close to the transmitter). Approximately 30 dB of receiver attenuation can be added by setting the Attenuation (ATT) bit. This limits data reception to devices at very short ranges. Disabling AGC and enabling LNA is recommended, unless receiving from a device using external PA. When the device is in receive mode the RSSI_ADR register returns the relative signal strength of the on-channel signal power. When receiving, the device automatically measures and stores the relative strength of the signal being received as a five bit value. An RSSI reading is taken automatically when the SoP is detected. In addition, a new RSSI reading is taken every time the previous reading is read from the RSSI_ADR register, allowing the background RF energy level on any given channel to be easily measured when RSSI is read while no signal is being received. A new reading can occur as fast as once every 12 s.
Nominal Frequency: 12 MHz Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: 30 ppm Series Resistance: <60 ohms Load Capacitance: 10 pF Drive Level: 100 W
Power Management
The operating voltage of the device is 1.8V to 3.6V DC, which is applied to the VBAT pin. The device can be shut down to a fully static sleep mode by writing to the FRC END = 1 and END STATE = 000 bits in the XACT_CFG_ADR register over the SPI interface. The device enters sleep mode within 35 s after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing the packet transmission or reception. When in sleep mode, the on-chip oscillator is stopped, but the SPI interface remains functional. The device wakes from sleep mode automatically when the device is commanded to enter transmit or receive mode. When resuming from sleep mode, there is a short delay while the oscillator restarts. The device can be configured to assert the IRQ pin when the oscillator has stabilized.
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CYRF7936
Application Examples
Figure 9. Recommended Circuit for Systems where VBAT 2.4V
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CYRF7936
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CYRF7936
Table 3. Recommended BoM for Systems where VBAT 2.4V Item Qty 1 2 3 4 5 6 7 8 1 1 1 1 1 2 1 6 NA 730-10012 730-11955 730-11398 730R-13322 730-13037 730-13400 730-13404 CY Part Number Reference ANT1 C1 C3 C4 C5 C12,C7 C8 Description Manufacturer Mfr Part Number NA ECJ-0EC1H150J C0402C209C5GAC TU ECJ-0EC1H1R5C GRM155R60J474K E19D C0805C106K9PAC TU ECJ-0EB0J105M 0402YD473KAT2A 2.5GHZ H-STUB WIGGLE ANTENNA NA FOR 32MIL PCB CAP 15PF 50V CERAMIC NPO 0402 Panasonic CAP 2.0 PF 50V CERAMIC NPO 0402 Kemet CAP 1.5PF 50V CERAMIC NPO 0402 PANASONIC SMD CAP CER .47UF 6.3V X5R 0402 Murata
CAP CERAMIC 10UF 6.3V X5R 0805 Kemet CAP 1 uF 6.3V CERAMIC X5R 0402 Panasonic AVX
C9,C10,C11, CAP 0.047 uF 50V CERAMIC X5R C13,C15,C1 0402 6 C17 D1 J1 L1 L2 L3 R1 R2 U1 Y1 PCB LABEL1 LABEL2
9 10 11 12 13 14 15 16 17 18 19 20 21
1 1 1 1 1 1 1 1 1 1 1 1 1
730R-11952 800-13317 420-11976 800-13401 800-11651 800-10594 630-11356 610-13402 CYRF7936-40LFXC 800-13259 PDCR-9515 REV01 920-11206 920-51500 REV01
CAP .10UF 10V CERAMIC X5R 0402 Kemet DIODE SCHOTTKY 0.5A 40V SOT23 DIODES INC CONN HEADER 12 PIN 2MM GOLD Hirose Electric Co. LTD. INDUCTOR 22NH 2% FIXED 0603 SMD INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD COIL 10UH 1100MA CHOKE 0805
C0402C104K8PAC TU BAT400D-7-F DF11-12DP-2DSA(0 1)
Panasonic - ECG ELJ-RE22NGF2 Panasonic - ECG ELJ-RF1N8DF Newark 30K5421 9C08052A1R00FK HFT CYRF7936-40LFXC GF-1200008 PDCR-9515 REV01
RES 1.00 OHM 1/8W 1% 0805 SMD Yageo RES 47 OHM 1/16W 5% 0402 SMD
Panasonic - ECG ERJ-2GEJ470X
IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress Semiconductor CRYSTAL 12.00MHZ HC49 SMD PRINTED CIRCUIT BOARD Serial Number PCA # eCERA Cypress Semiconductor
121R-51500 REV01
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5V C12
0402
VCC
VCC C5
0402
22 49
8 6 38
33
40
3 7 16
U2 VIO VDD VDD
IND0603
5V
0402
35
VBAT2 VBAT1 VBAT0
VREG
J1 TP1 RST 34 RST
IND0402
C17 0.47 uFd C1 10 22 nH
0402
VCC1 VCC2 VCC3
VBUS DM DP GND S1 S2 24 24 DM DP RFp RFn 1.8 nH C3 PACTL XTAL 1 30 PACTL TP2 2.0 pFd
0402
1 2 3 4 5 6 RFbias 11 13 L2 15 pFd
0402
0402
R4 zero
0402
NO LOAD
19 50
CY8C24794-24LFXI
VSS VSS
GND1
12
5V D1 R8 1 GR RD LED Green Red 5V S1 SW1 VCC 1A 1B SW PUSHBUTTON 2A 2B KR 4 nLED2 KG 2 3 R9
0402 0402
RED = USB ACTIVITY GREEN = RF ACTIVITY
620 620 nLED1
0402
C6 0.047 uFd
0402
C7 0.047 uFd
0402
C8 0.047 uFd
41
E-PAD
Power Supply
VCC U3 1 VIN EN
0805
5V
VOUT PYBASS 2.2 uFd TPS79133 2
0402
5 4 C15 0.01 uFd C14
C13 3 GND
Figure 10. Recommended Circuit for Systems where VBAT is 2.4V - 3.6V (PMU Disabled)
0805
4.7 uFd
0402
0402
LP_nSS R6 LP_IRQ 1K R5 SCK MISO 1K CLKOUT R7 MOSI 1K TP3 26 IRQ LP_IRQ
0402
0402
USB A RA PLUG P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7 TP4 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 R3 37 L/D NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 RESV NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 19 20 21 22 23 31 32 36 39 2 4 5 9 14 15 17 18 XOUT 29 RST CLKOUT TV1 Y1 40 2 42 1 43 56
0402
0603
VBUS DM DP L1 21 20 R10 R11 100 100 25 18 25 17 22 16 28 15 nLED2 24 25 27 28 SS SCK MOSI MISO nLED1 LP_nSS SCK MOSI MISO
0603
R1 R2
SW1 P0_1
C4 1.5 pFd
P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7
45 54 46 53 47 52 40 51
12 MHz Crystal
0402
C9 0.047 uFd
0402
C10 0.047 uFd
0402
C11 0.047 uFd
1 2
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1500 pFd 0.47 uFd VCC U1 CYRF7936 ANT1 WIGGLE 32
CYRF7936
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CYRF7936
Table 4. Recommended BoM for Systems where VBAT is 2.4V - 3.6V (PMU disabled) Item Qty CY Part Number Reference 1 2 3 4 5 6 1 1 1 1 1 6 NA 730-10012 730-11955 730-11398 730-13322 730-13404 ANT1 C1 C3 C4 C5 Description 2.5GHZ H-STUB WIGGLE ANTENNA FOR 32MIL PCB CAP 15PF 50V CERAMIC NPO 0402 CAP 2.0 PF 50V CERAMIC NPO 0402 CAP 1.5PF 50V CERAMIC NPO 0402 SMD CAP 0.47 uF 6.3V CERAMIC X5R 0402 Manufacturer NA Panasonic Kemet PANASONIC Murata AVX NA ECJ-0EC1H150J C0402C209C5GACTU ECJ-0EC1H1R5C GRM155R60J474KE19D 0402YD473KAT2A Mfr Part Number
C6,C7,C8, CAP 0.047 uF 16V CERAMIC X5R 0402 C9,C10, C11 C12 C13 C14 CAP 1500PF 50V CERAMIC X7R 0402 CAP CERAMIC 4.7UF 6.3V XR5 0805 CAP CER 2.2UF 10V 10% X7R 0805
7 8 9
1 1 1
730-11953 730-13040 730-12003
Kemet Kemet
C0402C152K5RACTU C0805C475K9PACTU
Murata GRM21BR71A225KA01L Electronics North America LITEON ACON LTST-C155KGJRKT UAR72-4N5J10
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 1 1 1 2 1 3 2 2 1 1 1 1 1
800-13333 420-13046 800-13401 800-11651 610-10037 610-10343 610-10016 610-13472 610-10684 200-13471
D1 J1 L1 L2 R1, R2 R4 R9,R8 R10, R11 S1
LED GREEN/RED BICOLOR 1210 SMD CONN USB PLUG TYPE A PCB SMT INDUCTOR 22NH 2% FIXED 0603 SMD INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD RES 24 OHM 1/16W 5% 0603 SMD RES ZERO OHM 1/16W 0402 SMD
Panasonic - ECG ELJ-RE22NGF2 Panasonic - ECG ELJ-RF1N8DF Panasonic - ECG ERJ-3GEYJ240V Panasonic - ECG ERJ-2GE0R00X
R5, R6, R7 RES CHIP 1K OHM 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ102X RES CHIP 620 OHM 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ621X RES CHIP 100 OHM 1/16W 5% 0402 SMD Phycomp USA Inc IC, 2.4 GHz CyFi Transceiver QFN-40 PSoC Mixed Signal Array CRYSTAL 12.00MHZ HC49 SMD Serial Number Cypress Semiconductor Cypress Semiconductor eCERA XXXXXX 9C1A04021000FLHF3
SWITCH LT 3.5MMX2.9MM 160GF SMD Panasonic - ECG EVQ-P7J01K CYRF7936 Rev A5 CY8C24794-24LFXI GF-1200008
CYRF7936-40LFC U1 CY8C24794-24LF U2 XI 800-13259 Y1 LABEL1
Document #: 001-48013 Rev. **
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CYRF7936
Register Descriptions
All registers are read and writable, except where noted. Registers may be written to or read from individually or in sequential groups. Table 5. Register Map Summary
Address
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x26 0x27 0x28 0x29 0x32 0x35 0x39 Register Files 0x20 0x21 0x22 0x23 0x24 0x25
Mnemonic
CHANNEL_ADR TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR RX_CFG_ADR RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR XTAL_CFG_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_AD R ANALOG_CTRL_ADR TX_BUFFER_ADR RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR
b7
Not Used
b6
b5
b4
b3
b2
b1
b0
Default[1] Access[1]
-1001000 00000000 00000011 --000101 -------00000111 10010-10 --------------00000000 00000000 10100000 000--100 00000000 0000---1-000000 10100101 ----0100 ---01010 0-100000 10100100 00000000 00000000 --------------11111111 11111111 00000000 ----0000 00000--0 000000000000000 00000000 00000000 00000000 00000000 00000011 00000000 00000000 --------------Note 2 Note 3 Note 4 NA -bbbbbbb bbbbbbbb bbbbbbbb --bbbbbb rrrrrrrr bbbbbbbb bbbbb-bb brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb bbb--bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb ----bbbb ---bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb ----bbbb wwwww--w bbbbbbbbbbbbbbb wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr
TX GO Not Used OS IRQ RX GO AGC EN RXOW IRQ RX ACK
TX CLR Not Used LV IRQ RSVD LNA SOPDET IRQ PKT ERR
TXB15 IRQEN DATA CODE LENGTH TXB15 IRQ RXB16 IRQEN ATT RXB16 IRQ EOP ERR
Channel TX Length TXB8 TXB0 IRQEN IRQEN
TXBERR IRQEN
TXC IRQEN
TXE IRQEN
PMU EN
LVIRQ EN
XOUT FN IRQ OD IRQ POL XOUT OP ACK EN SOP EN Not Used Not Used SOP HEN MISO OP Not Used SOP LEN Not Used Not Used Not Used
PMU Mode Force XSIRQ EN MISO OD PACTL OP FRC END LEN EN Not Used Not Used LNA HINT
Not Used RSVD ACK RX ACK TX RSVD RSVD RSVD RSVD
Not Used RSVD RXTX DLY FRC PRE RSVD RSVD RSVD RSVD
Not Used FRC SEN MAN RXACK RSVD RSVD RSVD RSVD ABORT EN
DATA MODE PA SETTING TXB8 TXB0 TXBERR TXC TXE IRQ IRQ IRQ IRQ IRQ RXB8 RXB1 RXBERR RXC RXE IRQEN IRQEN IRQEN IRQEN IRQEN FAST TURN HILO EN Not Used RXOW EN VLD EN RXB8 RXB1 RXBERR RXC RXE IRQ IRQ IRQ IRQ IRQ CRC0 Bad CRC RX Code RX Data Mode RX Count RX Length PFET LVI TH PMU OUTV disable Not Used Not Used FREQ XOUT OD PACTL OD PACTL SPI 3PIN IRQ GPIO GPIO IRQ OP XOUT IP MISO IP PACTL IP IRQ IP END STATE ACK TO SOP TH Not Used TH32 TH64 RSSI EOP CRC SEED LSB CRC SEED MSB CRC LSB CRC MSB CRC LSB CRC MSB STRIM LSB Not Used STRIM MSB FRC AWAKE Not Used Not Used RST FRC RXDR DIS CRC0 DIS RXCRC ACE Not Used MAN TXACK OVRD ACK DIS TXCRC RSVD TX INV RSVD START DLY RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD RSVD RSVD RSVD RXF RSVD RSVD RSVD RSVD RSVD RSVD AUTO_CAL_TIME AUTO_CAL_OFFSET RSVD RSVD RSVD RX INV ALL SLOW
RSVD
RSVD
RSVD
TX Buffer File RX Buffer File SOP Code File Data Code File Preamble File MFG ID File
Notes 1. b = read/write; r = read only; w = write only; `-' = not used, default value is undefined. 2. SOP_CODE_ADR default = 0x17FF9E213690C782. 3. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F. 4. PREAMBLE_ADR default = 0x333302. The count value must be great than 4 for DDR and greater than 8 for SDR 5. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode. The PMU, GPIOs, and RSSI registers can be accessed in Active Tx and Rx mode. 6. EOP_CTRL_ADR[6:4] must never have the value of "000", that is, EOP Hint Symbol count must never be "0" 7. PFET Bit: Setting this bit to "1" disables the FET, therefore safely allowing Vbat to be connected to a separate reference from Vcc when the PMU is disabled to the radio.
Document #: 001-48013 Rev. **
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CYRF7936
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied.. -55C to +125C Supply Voltage on any power supply pin relative to VSS .................................................-0.3V to +3.9V DC Voltage to Logic Inputs[8] ................... -0.3V to VIO +0.3V DC Voltage applied to Outputs in High-Z State......................................... -0.3V to VIO +0.3V
Static Discharge Voltage (Digital)[9] ........................... >2000V Static Discharge Voltage (RF)[9] ................................. 1100V Latch-Up Current .....................................+200 mA, -200 mA
Operating Conditions
VCC .....................................................................2.4V to 3.6V VIO ......................................................................1.8V to 3.6V VBAT ....................................................................1.8V to 3.6V TA (Ambient Temperature Under Bias) ............. 0C to +70C Ground Voltage.................................................................. 0V FOSC (Crystal Frequency)............................ 12MHz 30 ppm
DC Characteristics
(T = 25C, VBAT = 2.4V, PMU disabled, fOSC = 12.000000 MHz)
Parameter
VREG[10] VREG[10] VIO[11] VCC VOH1 VOH2 VOL VIH VIL IIL CIN ICC (GFSK)[13] VBAT
Description
Battery Voltage PMU Output Voltage PMU Output Voltage VIO Voltage VCC Voltage Output High Voltage Condition 1 Output High Voltage Condition 2 Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Pin Input Capacitance Average TX ICC, 1 Mbps, slow channel Sleep Mode ICC Sleep Mode ICC Radio off, XTAL Active ICC during Synth Start ICC during Transmit ICC during Transmit ICC during Transmit ICC during Receive ICC during Receive PMU Boost Converter Efficiency Average PMU External Load current Average PMU External Load current 0-70C 0-70C 2.4V mode 2.7V mode
Conditions
At IOH = -100.0 A At IOH = -2.0 mA At IOL = 2.0 mA
Min 1.8 2.4 2.7 1.8 2.4[12] VIO - 0.2 VIO - 0.4
0.7VIO 0
Typ
2.43 2.73
Max 3.6
3.6 3.6 VIO VIO 0 0.45 VIO 0.3VIO 0.26 3.5 0.87 1.2 0.8 10 31.4 1.0 8.4 20.8 26.2 34.1 18.4 21.2 81 15 10 +1 10
0 < VIN < VIO except XTAL, RFN, RFP, RFBIAS PA = 5, 2 way, 4 bytes/10 ms
-1
ICC (32-8DR)[13] Average TX ICC, 250 kbps, fast channel PA = 5, 2 way, 4 bytes/10 ms ISB[14] ISB[14] PMU enabled XOUT disabled PA = 5 (-5 dBm) PA = 6 (0 dBm) PA = 7 (+4 dBm) LNA off, ATT on LNA on, ATT off VBAT = 2.5V, VREG = 2.73V, ILOAD = 20 mA VBAT = 1.8V, VREG = 2.73V, 0-50C, RX Mode VBAT = 1.8V, VREG = 2.73V, 50-70C, RX Mode
IDLE ICC Isynth TX ICC TX ICC TX ICC RX ICC RX ICC Boost Eff ILOAD_EXT ILOAD_EXT
Unit V V V V V V V V V V A pF mA mA A A mA mA mA mA mA mA mA %
mA mA
Notes 8. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed. 9. Human Body Model (HBM). 10. VREG depends on battery input voltage. 11. In sleep mode, the IO interface voltage reference is VBAT. 12. In sleep mode, VCC min. can be as low as 1.8V. 13. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK handshake. Device is in sleep except during this transaction. 14. ISB is not guaranteed if any IO pin is connected to voltages higher than VIO.
Document #: 001-48013 Rev. **
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CYRF7936
AC Characteristics
The AC Characteristics of CYRF7936 follow[12] Table 6. SPI Interface[16] Parameter tSCK_CYC tSCK_HI tSCK_LO tDAT_SU tDAT_HLD tDAT_VAL tDAT_VAL_TRI tSS_SU tSS_HLD tSS_PW tSCK_SU tSCK_HLD tRESET SPI Clock Period SPI Clock High Time SPI Clock Low Time SPI Input Data Setup Time SPI Input Data Hold Time SPI Output Data Valid Time SPI Output Data Tri-state (MOSI from Slave Select Deassert) SPI Slave Select Setup Time before first positive edge of SCK SPI Slave Select Hold Time after last negative edge of SCK SPI Slave Select Minimum Pulse Width SPI Slave Select Setup Time SPI SCK Hold Time Minimum RST Pin Pulse Width Figure 11. SPI Timing
tSCK_CYC SCK tSCK_SU nSS tSS_SU tDAT_SU MOSI input tDAT_VAL MISO tDAT_VAL_TRI tDAT_HLD tSS_HLD tSCK_HI tSCK_LO tSCK_HLD
Description
Min 238.1 100 100 25 10 0
[17]
Typ
Max
Unit ns ns ns ns ns
50 20
ns ns ns ns ns ns ns ns
10 10 20 10 10 10
MOSI output
Notes 15. AC values are not guaranteed if voltage on any pin exceeding VIO. 16. CLOAD = 30 pF 17. SCK must start low at the time SS# goes LOW, otherwise the success of SPI transactions are not guaranteed.
Document #: 001-48013 Rev. **
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CYRF7936
RF Characteristics
Table 7. Radio Parameters Parameter Description RF Frequency Range Note 18 Receiver (T = 25C, VCC = 3.0V, fOSC = 12.000000 MHz, BER < 1E-3) Sensitivity 125 kbps 64-8DR BER 1E-3 Sensitivity 250 kbps 32-8DR Sensitivity Sensitivity GFSK LNA Gain ATT Gain Maximum Received Signal RSSI Value for PWRin -60 dBm RSSI Slope Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) Adjacent (1 MHz) channel selectivity C/I 1 MHz Adjacent (2 MHz) channel selectivity C/I 2 MHz Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz Out-of-Band Blocking 30 MHz-12.75 MHz[19] Intermodulation Receive Spurious Emission 800 MHz 1.6 GHz 3.2 GHz Transmitter (T = 25C, VCC = 3.0V) Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power RF Power Control Range RF Power Range Control Step Size Frequency Deviation Min Frequency Deviation Max Error Vector Magnitude (FSK error) Occupied Bandwidth Transmit Spurious Emission (PA = 7) In-band Spurious Second Channel Power (2 MHz) In-band Spurious Third Channel Power (>3 MHz) -38 -44 dBm dBm Seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 >0 dBm -6 dBc, 100 kHz ResBW 500 PA = 7 PA = 6 PA = 5 PA = 0 +2 -2 -7 4 0 -5 -35 39 5.6 270 323 10 876 +6 +2 -3 dBm dBm dBm dBm dB dB kHz kHz %rms kHz 100 kHz ResBW 100 kHz ResBW 100 kHz ResBW -79 -71 -65 dBm dBm dBm C = -60 dBm C = -60 dBm C = -60 dBm C = -67 dBm C = -67 dBm C = -64 dBm, f = 5,10 MHz 9 3 -30 -38 -30 -36 dB dB dB dB dBm dBm LNA On LNA On -15 BER 1E-3 CER 1E-3 BER 1E-3, ALL SLOW = 1 -80 Conditions Min 2.400 -97 -93 -87 -84 22.8 -31.7 -6 21 1.9 Typ Max 2.497 Unit GHz dBm dBm dBm dBm dB dB dBm Count dB/Count
Notes 18. Subject to regulation. 19. Exceptions F/3 & 5C/3.
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CYRF7936
Table 7. Radio Parameters (continued) Parameter Description Non-Harmonically Related Spurs (800 MHz) Non-Harmonically Related Spurs (1.6 GHz) Non-Harmonically Related Spurs (3.2 GHz) Harmonic Spurs (Second Harmonic) Harmonic Spurs (Third Harmonic) Fourth and Greater Harmonics Power Management (Crystal PN# eCERA GF-1200008) Crystal Start to 10ppm Crystal Start to IRQ Synth Settle Synth Settle Synth Settle Link Turnaround Time Link Turnaround Time Link Turnaround Time Link Turnaround Time Max Packet Length XSIRQ EN = 1 Slow channels Medium channels Fast channels GFSK 250 kbps 125 kbps <125 kbps <60 ppm crystal-to-crystal 0.7 0.6 270 180 100 30 62 94 31 40 1.3 ms ms s s s s s s s bytes Conditions Min Typ -38 -34 -47 -43 -48 -59 Max Unit dBm dBm dBm dBm dBm dBm
Document #: 001-48013 Rev. **
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CYRF7936
Typical Operating Characteristics
The typical operating characteristics of CYRF7936 follow[20]
Transmit Power vs. Temperature (Vcc = 2.7v) 6 4 Output Power (dBm) 2 0 -2 -4 -6 -8 -10 -12 -14 0 20 40 Temp (deg C) 60 6 4 Output Power (dBm) 2 0 -2 -4 -6 -8 -10 -12 -14 2.4 2.6 2.8 Transmit Power vs. Vcc (PMU off)
Transmit Power vs. Channel 6
PA7 PA6
PA7
Output Power (dBm)
4 2 0 -2 -4 -6 -8 -10 -12 -14
3 3.2 3.4 3.6
PA7 PA6
PA6
PA5
PA5
PA5
PA4
PA4
PA4
0
20
40 Channel
60
80
Vcc
Typical RSSI Count vs Input Power
Average RSSI vs. Temperature (Rx signal = -70dBm) 19 18 20 19 18 RSSI Count 17 16 15 14 13 12 13 11 0 20 40 Temp (deg C) 60 10 2.4 2.6
Average RSSI vs. Vcc (Rx signal = -70dBm)
32
24 RSSI Count RSSI Count
17
16
LNA ON LNA OFF ATT ON LNA OFF
16 15 14
8
0 -120
12 -100 -80 -60 -40 -20 Input Power (dBm)
2.8
3 Vcc
3.2
3.4
3.6
RSSI vs. Channel (Rx signal = -70dBm) 18
Rx Sensitivity vs. Vcc (1Mbps CER) -80 Receiver Sensitivity (dBm) -82 -84 -86 -88 -90 -92 -94 2.4
Rx Sensitivity vs. Temperature (1Mbps CER) -80 Receiver Sensitivity (dBm) -82 -84 -86 -88 -90 -92 -94
16 14 RSSI Count 12 10 8 6 4 2 0 0 20 40 Channel 60 80
CER
CER
8DR32
8DR32
2.6
2.8
3 Vcc
3.2
3.4
3.6
0
20
40 Temp (deg C)
60
Receiver Sensitivity vs. Frequency Offset -80 -82 Receiver Sensitivity (dBm) Receiver Sensitivity (dBm) -83 -85 -87 -89 -91 -93 -95 -100 -50 0 Crystal Offset (ppm) 50 100 150 0 10 20 -84 -86 -88 -90 -92 -94
Receiver Sensitivity vs Channel (3.0v, Room Temp) -81
Carrier to Interferer (Narrow band, LP modulation) 20.0 10.0 0.0
GFSK
GFSK
CER
C/I (dB)
-10.0 -20.0 -30.0 -40.0
8DR64
-96 -98 -150
8DR32
-50.0 -60.0 -10
-5
0
5
10
30
40 Channel
50
60
70
80
Channel Offset (MHz)
Note 20. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read. Cross-checking RSSI with LNA off/on is recommended for accurate readings.
Document #: 001-48013 Rev. **
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CYRF7936
Typical Operating Characteristics (continued)
BER vs. Data Threshold (32-8DR) (SOP Threshold = 5, C38 slow) 10 1 0.1 0.01 0.001 0.0001 0.00001 -100
GFSK vs. BER (SOP Threshold = 5, C38 slow) 100 10 1 %BER 0.1 0.01 0.001 0.0001 0.00001 -100
0 Thru 7
%BER
GFSK
-80 -60 -40 -20 0
-95
-90
-85
-80
-75
-70
Input Power (dBm)
Input Power (dBm)
ICC RX (LNA OFF) 21 OPERATING CURRENT (mA) OPERATING CURRENT (mA) 20.5 20 19.5 19 18.5 18 17.5 17 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 25 24.5
ICC RX (LNA ON) 9.2 9.1 9 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8 7.9 7.8 0 5
ICC RX SYNTH
3.3V 3.0V 2.7V 2.4V
24 23.5 23 22.5 22 21.5 21 20.5 20 19.5 19 0 5
3.3V 3.0V 2.7V 2.4V
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
ICC TX SYNTH 9.2 9.1 9 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8 7.9 7.8 0 5 17 OPERATING CURRENT (mA) 16.5 16 15.5 15 14.5 14 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 0 5
ICC TX @ PA0 17.5 OPERATING CURRENT (mA)
ICC TX @ PA1
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
17 16.5 16 15.5 15 14.5 14
3.3V 3.0V 2.7V 2.4V
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
ICC TX @ PA2 18 OPERATING CURRENT (mA) 17.5 17 16.5 16 15.5 15 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 19
ICC TX @ PA3 20.5 OPERATING CURRENT (mA)
ICC TX @ PA4
3.3V 3.0V 2.7V 2.4V
OPERATING CURRENT (mA)
18.5 18 17.5 17 16.5 16 15.5 0
3.3V 3.0V 2.7V 2.4V
20 19.5 19 18.5 18 17.5 17 16.5
3.3V 3.0V 2.7V 2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
Document #: 001-48013 Rev. **
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CYRF7936
Typical Operating Characteristics (continued)
ICC TX @ PA5 23.5 OPERATING CURRENT (mA) OPERATING CURRENT (mA) 23 22.5 22 21.5 21 20.5 20 19.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 30 OPERATING CURRENT (mA) ICC TX @ PA6 40.5 40 39.5 39 38.5 38 37.5 37 36.5 36 35.5 35 34.5 34 33.5 33 32.5 0 ICC TX @ PA7
3.3V 3.0V 2.7V 2.4V
29.5 29 28.5 28 27.5 27 26.5 26 25.5 25 24.5 0
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
AC Test Loads and Waveforms for Digital Pins
Figure 12. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
OUTPUT 30 pF INCLUDING JIG AND SCOPE OUTPUT 5 pF
DC Test Load
VCC OUTPUT R2 R1
Max
INCLUDING JIG AND Typical SCOPE ALL INPUT PULSES
Parameter R1 R2 RTH VTH VCC
1071 937 500 1.4 3.00
Unit V V
VCC GND Rise time: 1 V/ns Equivalent to: OUTPUT
90% 10%
90% 10% Fall time: 1 V/ns
THEVENIN EQUIVALENT RTH VTH
Ordering Information
Table 8. Ordering Information Part Number CYRF7936-40LFXC Radio Transceiver Package Name Package Type 40 QFN 40 Quad Flat Package No Leads Pb-Free CYRF7936 Operating Range Commercial
Document #: 001-48013 Rev. **
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CYRF7936
Package Description
Figure 13. 40-Pin Pb-Free QFN 6 x 6 mm LY40
SOLDERABLE EXPOSED PAD
NOTES: 1. HATCH IS SOLDERABLE EXPOSED AREA
2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.086g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE
UNLESS OTHERWISE SPECIFIED
(SUBCON Punch Type PKG WITH 3.50X3.50 EPAD)
DESIGNED BY DRAWN CHK BY APPROVED BY APPROVED BY DATE DATE
PART # LF40A LY40A
DESCRIPTION STANDARD PB-FREE
ALL DIMENSIONS ARE IN INCHES [MILLIMETERS] STANDARD TOLERANCES ON: DECIMALS ANGLES + + .XX + .XXX + .XXXX -
MLA
07/10/08
DATE
CYPRESS COMPANY CONFIDENTIAL
TITLE
DATE DATE
40LD QFN 6 X 6MM PACKAGE OUTLINE (SUBCON PUNCH TYPE PKG with 3.50 X 3.50 EPAD)
PART NO. DWG NO
MATERIAL
SIZE
001-12917 *A REV
*A
SEE NOTES
001-12917
The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 3.5 mm x 3.5 mm (width x length).
Document #: 001-48013 Rev. **
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CYRF7936
Document History Page
Description Title: CYRF7936 2.4 GHz CyFiTM Transceiver Document #: 001-48013 Rev. ** REV.
**
ECN
2557501
Orig. of Change
KKU/AESA
Submission Date
09/10/08 New Data Sheet
Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-48013 Rev. **
Revised September 10, 2008
Page 21 of 21
CyFi, WirelessUSB, PSoC, and enCoRe are trademarks of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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